ERTS 2022




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Ahmad-Reza Sadeghi, TU Darmstadt, Germany

Wednesday 30 March, 2022 - Auditorium 10:30-11:30 am

Ahmad-Reza Sadeghi is a professor of Computer Science and the head of the System Security Lab at Technical University of Darmstadt, Germany. He has been leading several Collaborative Research Labs with Intel since 2012, and with Huawei since 2019. 
He has studied both Mechanical and Electrical Engineering and holds a Ph.D. in Computer Science from the University of Saarland, Germany. Prior to academia, he worked in R&D of IT-enterprises, including Ericsson Telecommunications. He has been continuously contributing to security and privacy research field. He was Editor-In-Chief of IEEE Security and Privacy Magazine, and currently serves on the editorial board of ACM TODAES, ACM TIOT, and ACM  DTRAP. For his influential research on Trusted and Trustworthy Computing he received the renowned German “Karl Heinz Beckurts” award. This award honors excellent scientific achievements with high impact on industrial innovations in Germany. In 2018, he received the ACM SIGSAC Outstanding Contributions Award for dedicated research, education, and management leadership in the security community and for pioneering contributions in content protection, mobile security and hardware-assisted security. In 2021, he was honored with Intel Academic Leadership Award at USENIX Security conference for his influential research on cybersecurity and in particular on hardware-assisted security.

Presentation title :
In Hardware we Trust?: The Promises, Struggle, Challenges and Future of Trusted Computing

The large attack surface of applications and commodity operating systems has motivated the research, development and deployment of hardware-assisted security extensions to computing platformsto significantly improve the security of applications and sensitive data against various software-based attacks. However, the current trusted computing architectures seem to struggle with keeping their promises, particularly in the face of cross-layer attacks that allow unprivileged software to exploit hardware design and implementation flaws, as recently shown by, e.g., Meltdown, Spectre, and alike. Cross-layer attacks reach far beyond exploiting micro-architectural flaws and constitute a fundamental paradigm shift, disrupting traditional threat models that have mainly focused on software-only vulnerabilities and often (unjustifiably) assumed that the underlying hardware is correct and trustworthy.

In this talk, we present a brief overview of Trusted Computing landscape, its promises, pitfalls and opportunities. We then discuss the recent trends in building open enclave architectures (e.g., RISC-V-based), including our own work in collaboration with industry partners, aiming to address the shortcomings of the existing solutions. We also briefly discuss the insights we gained on cross-layer attacks and hardware vulnerability detection in the course of the world’s largest hardware security competition that we have been co-organizing with industry and academic partners since 2018. We conclude with future directions for trusted computing and the corresponding challenges. 

Christophe Honvault, ESA, THE NETHERLANDS 

Thursday 31 March, 2022 - Auditorium - 08:30 - 09:30 am


Christophe Honvault is responsible of the Software Technology section in the Software Systems division at ESA/ESTEC.

He is leading a team of experts in the domain of new technologies to evaluate their use in the domain of the division, i.e. the development of space software and their ground software support.

The list of technologies that are currently evaluated are related to Requirements engineering (Ontology), data modelling and specification, formal methods, Big Data, Cybersecurity, Quantum Computing and of course all the numerous applications of Artificial Intelligence.

He is responsible of an In-Orbit Demonstration activity of an AI-based fault detection application planned to fly on the HERA spacecraft.

He is the convenor of the ECSS Software standard (ECSS-E-ST-40C) that is currently under revision and co-chair of the ESA Board for Software Standardisation and Control.


Presentation title : 
The 5 Ws and 1 H of autonomous space systems

The performance of first processors used in space was limited as well as the amount of their memory. Only critical functions were implemented and all operations were planned on ground by operators. In the last three decades, the evolution of space processor capabilities has been very significant, growing from one to several hundred million operations per second allowing an increase of the number and complexity of functions that can be executed on-board. Nevertheless, the change in mentality of institutional customers, operators and project managers is taking time, slowing down the introduction of autonomy concepts and functions in space systems.

In this keynote, we present the evolution of space systems from automation to autonomy. We then address the benefits and challenges of the introduction of autonomy in critical space systems by proposing some solutions with concrete examples to the five W questions. Why implementing autonomy in space systems? When can a space system benefit from being autonomous? Who benefits from autonomous space systems? Where to implement autonomy? What are the current technologies and architectures? As a conclusion, we suggest some actions on How to achieve a dependable critical autonomous space system.




Abstract of Regular &
Short Paper submission (4 pages)
: Sept.5th, 2021 

Submission deadline
extended to October 3rd, 2021 (any time on earth)

Acceptance Notification : Nov. 18th, 2021

Regular Paper for review (10 pages) : Jan. 9th, 2022

Final Paper (Short and Regular) :
Jan. 30th, 2022

Congress (new dates): June 1st to 2nd, 2022









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